A Time-Digital Converter (TDC) is widely applied in integrated circuits and mainly used to provide phase discrimination for a digital phase-locked loop (DPLL). In addition, in many application scenarios, such as nuclear medicine imaging, laser ranging, and half life testing of particles in high energy physics, etc., a TDC is used to discriminate minute time (phase) differences. A TDC is implemented with full digital technology, and has good portability as the size is decreased. Moreover, full digital TDC circuits have better noise immunity and lower power consumption. Both the discrimination accuracy and the lock time of TDCs are greatly improved compared with conventional frequency and phase discriminators, since TDCs quantize time (phase) differences into digital outputs.
A TDC is a time (phase) difference discrimination circuit which replaces conventional phase discriminators. In DPLL, the digital control words output by a TDC reflects the time difference between the rising edges of two input signals and directly drives the oscillator to adjust the frequency. Therefore, the requirement for discrimination accuracy of a TDC is very high. One common structure is a delay line TDC, in which a delay line is composed of a series of inverters with very low delay through series connections, wherein, one input signal is transmitted through the delay line, and is compared with another input signal after passing each stage of delay, so as to discriminate the time difference between the rising edges of the two signals. The resolution of a TDC with such a structure is equal to the delay time in each stage of delayer, and therefore highly depends on the manufacturing technology; meanwhile, the deviation is severe, and further improvement of resolution is limited.
Another implementation structure is a stochastic time-digital converter (STDC). In case the phases of two signals are close to each other, the judgment of the comparator may have indeterminacy, owing to the influence of PVT and mismatch of components. The error resulting from the indeterminacy follows Gaussian distribution. A number of identical comparators can be used to form an array, and the output from the comparators can be collected and analyzed, and thereby the information of the signal phase difference can be obtained. Such a structure can achieve very fine resolution and is highly tolerant to PVT. However, since the achievable resolution is directly related with the number of used comparators, a large number of comparators are required to improve the resolution; as a result, the power consumption, area and hardware cost will be inevitably increased.